Digital Design and prototyping Engineer

🧠 Contracting Role - All-Around Engineer (FPGA-based Prototyping Flow)

We are seeking a skilled all-around Engineer for contracting role, focused on enhancing existing FPGA-based prototyping flow. The ideal candidate will have experience in digital design and FPGA flow based on Xilinx Vivado and Synopsys HAPS.

You will work to design and validation teams to improve scripts, build images and execute basic acceptance testing of the generated images. You'll have the ability to assess quality of timing reports and propose improvements either to design, constraints or to the flow itself.

You'll have responsibility for maintaining System Verilog testbenches used for issue analysis and redact technical documentation on FPGA emulation of supported IP variants.

🧾 Responsabilities :

• Enhance existing FPGA-based prototypes using Synopsys HAPS-100 and CEVA platforms (Virtex-7).
• Analysis of synthesis, place-and-route and timing results for large-scale designs.
• Basic validation of FPGA prototypes and ability to plan and instrument tools for debug (Synopsys Identify, Vivado ILA).
• Collaborate with ASIC/SOC design teams to ensure FPGA conformity to specs and functionality.
• Contribute to FPGA build automation using scripting languages (Shell, TCL, Python). Maintain or develop testbenches (System Verilog) in support to FPGA debug.
• Maintain and redact technical documentation covering the FPGA emulation (build flow, acceptance testing, architecture).

🎓 Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

5+ years of experience in digital design and ASIC/FPGA.

Proficiency in FPGA flow (synthesis, timing analysis, and debugging) on Xilinx (Vivado) and Synopsys (HAPS-100, ProtoCompiler).

Proficiency in Verilog/SystemVerilog.

Proficiency in scripting (TCL, Python, Shell) for tool automation.

Excellent analytical and problem-solving skills and capable of working in autonomy. Understanding of version control systems.

Good communication skills.

⭐ Preferred Qualifications

Preferred Qualifications:

• Experience with multi-FPGA partitioning with HAPS platforms.
• Experience with ProtoCompiler.
• Experience with ASIC/SOC design and verification flows.
• Exposure to ASIC synthesis in Design Compiler.
• Exposure to SVN version control.